1. Technical Field of the Invention
The present invention relates to electrode pads for external connection in a semiconductor integrated circuit device, and more particularly to the placement of zigzag-arranged electrode pads and lead interconnects running directly under the electrode pads, as well as the cross-sectional structure of the electrode pads.
2. Related Art
In recent years, with the progress of the digitalized society, higher-function, smaller-size and lower-cost semiconductor devices have been increasingly demanded. For lower-cost semiconductor devices, it is effective to increase the number of semiconductor chips taken from one wafer. Hence, along with the miniaturization of semiconductor devices, the chip area is increasingly reduced. With this reduction in chip area, together with increase in the number of pins resulting from the multifunction capability, it has become necessary to arrange electrode pads for external connection, placed in the peripheral portion of the semiconductor chip, at high density. The size of the electrode pads is already in a range any value below which is unavailable in consideration of the connectivity, pitch and reliability of wire bonds and bumps used for external connection and the pitch of probes used for testing. In view of this, there is implemented a semiconductor device in which electrode pads in the peripheral portion of a semiconductor chip are arranged zigzag, not in one row (see Japanese Laid-Open Patent Publication No. 10-74790, for example).
FIG. 9A is a plan view showing the structure of electrode pads of a first conventional semiconductor device, and FIG. 9B is an enlarged plan view of region D in FIG. 9A. FIG. 10A is an enlarged plan view showing the structure of electrode pads of a second conventional semiconductor device, and FIG. 10B is a cross-sectional view schematically illustrating occurrence of a crack in the second conventional semiconductor device.
As shown in FIGS. 9A and 9B, in the first conventional semiconductor device, the electrode pads are arranged zigzag in the peripheral portion of a semiconductor chip 111. Among the electrode pads, outer-row pads 121b are connected to an internal circuit 112 via respective lead interconnects 152. In the first conventional semiconductor device, however, it is necessary to arrange inner-row pads 121a apart from each other by the width of the lead interconnects 153, and this reduces the number of electrode pads allowed to be arranged per unit area.
To solve the above problem, as shown in FIG. 10A, lead interconnects 152 connected to outer-row pads 121b are made to run in a wiring layer lying directly under the inner-row pads 121a, so that the inner-row pads 121a and the lead interconnects 152 overlap each other as viewed from top. The number of electrode pads allowed to be arranged per unit area can therefore be increased.